jktstance
Newbie level 5
This in kind of a basic question, but I haven't been able to find an explanation as to WHY this happens. I am pretty sure higher input slews will add delay to an inverter, but I’m not sure about the inverter’s output slew.
What is the physics going on there? Where on the input slew does the output start to change? Say the input is rising. Does the output begin to transition when the input signal is VIL, VMid, VIH, or right when the input begins to transition? Depending on the definition, the output delay could be different and would affect also affect setup, hold, and short-circuit current.
I suspect a high slew means Vgs takes longer to increase, which increases the time for Id to increase, thus taking longer to charge the output capacitance.
What is the physics going on there? Where on the input slew does the output start to change? Say the input is rising. Does the output begin to transition when the input signal is VIL, VMid, VIH, or right when the input begins to transition? Depending on the definition, the output delay could be different and would affect also affect setup, hold, and short-circuit current.
I suspect a high slew means Vgs takes longer to increase, which increases the time for Id to increase, thus taking longer to charge the output capacitance.