How does input slew to an inverter affect output slew and delay?

[jktstance]

This in kind of a basic question, but I haven't been able to find an explanation as to WHY this happens. I am pretty sure higher input slews will add delay to an inverter, but I’m not sure about the inverter’s output slew.

What is the physics going on there? Where on the input slew does the output start to change? Say the input is rising. Does the output begin to transition when the input signal is VIL, VMid, VIH, or right when the input begins to transition? Depending on the definition, the output delay could be different and would affect also affect setup, hold, and short-circuit current.

I suspect a high slew means Vgs takes longer to increase, which increases the time for Id to increase, thus taking longer to charge the output capacitance.

 

[dick_freebird]

Every inverter has a linear region between
VTN and (VDD-VTP).

The slower you roll through that, the slower
you reach the full input drive strength to get
full output drive hence minimum prop delay
and transition time.

It's an easy thing to characterize in SPICE.

Timing models will (or should) declare an
input risetime range for which timing data
is valid. Outside of that you should get stuff
like synthesis warnings about net loading.

 

[jktstance]

Thanks, that's how I was imagining it when looking at waveforms. So high input slew translates to higher propagation delay and output slew.

A related question to that: does a high drive strength inverter improve the slew? That is, if the input slew is high, will a strong inverter yield a lower output slew? Once the input reaches the switching threshold, I think the inverter would be able to supply a lot of current to charge the output load, meaning a lower output transition time.

On the other hand, though, transistor current is proportional to Vgs, so if Vgs is rising slowly, Id is also increasing at a slow rate.

I can't seem to figure out which of the two it is. Or if it's both, maybe one effect dominates the other.