bageduke
Advanced Member level 4
Hi, everyone, I have a little bit special case of shift register design. Can someone give me a help?
Here I have two complementary clocks, voltage swing 0-3.3V, and internal logic is using -6V ~ 6V or even higher, PMOS and NMOS threshold voltages are about 2.5V(kind of strang process ).
Now I need to design fast shift register which may run at 54MHz or higher(up to 108MHz).
Since there are several hundred shift register have been used in the chip, if I really need clock level shifter, there are two solutions:
1)Use single high performance clock level shifter and use big buffer after it, then because of those hundreds of shift registers, capacitive load after the buffer will be huge and power consumption will be large.
2)Use separate simple clock level shifter in each shift register. It may decrease the power, but the level shifter should be very simple(for layout area), efficient, and fast.
Otherwise, is there any kind of shift register circuit topoloy that doesn't need level shifter?
Can someone give me a help? Or some circuit architectures to deal with this kind of issue?
Thanks a lot
Here I have two complementary clocks, voltage swing 0-3.3V, and internal logic is using -6V ~ 6V or even higher, PMOS and NMOS threshold voltages are about 2.5V(kind of strang process ).
Now I need to design fast shift register which may run at 54MHz or higher(up to 108MHz).
Since there are several hundred shift register have been used in the chip, if I really need clock level shifter, there are two solutions:
1)Use single high performance clock level shifter and use big buffer after it, then because of those hundreds of shift registers, capacitive load after the buffer will be huge and power consumption will be large.
2)Use separate simple clock level shifter in each shift register. It may decrease the power, but the level shifter should be very simple(for layout area), efficient, and fast.
Otherwise, is there any kind of shift register circuit topoloy that doesn't need level shifter?
Can someone give me a help? Or some circuit architectures to deal with this kind of issue?
Thanks a lot
