High fanout, but no timing violation. Must fix?

[vampiresan]

how to fix fanout violations

Hi guys,

A research question for myself.

If I have a clock which has high fan-out, but there is no timing violation, no transition time violation.
Do I still need to fix it?
Why?

Thanks
Vampie

 

[wkong_zhu]

timing violation

I think transition time should not be so large in that the clock tree will dissipate much power if transition time is long.

 

[RBB]

Possibly.

The transition time will be outside the look up table in the model. This may cause your silicon not to match simulation or STA.

 

[rameshsuthapalli]

Hi,

If you see the logfile of the PT it will give that the load of the following net has been taken as x (small) value compared to the actual fanout value for caluculating the delay of the net.because of which u may not fine the problem in timing but in the actual case the cell may not drive the signal properly.so place a tree on that net will match results with chip results.

Regards,
Ramesh.S

 

[onlymusic16]

i think you should do it.

I have seen where primetime, when goes out of the matrices in the .lib, extrapolates the numbers very badly.

 

[sam536]

you have to fix if u see any Fanout violations. Because your comprimising on fanout to reach your timing goals.

--Sam