Hierarchy question in cadence virtuoso

[yans123]

Hi,

I created hierarchy in Virtuoso 6.1.x
I created the transistors from scratch , I mean my basic cell is just
a transistor with pins because I want to simulate my basic transistor with some more adjustments to leakage currents and some reliability issues ,
and than I built my architecture with this basic cells .
My problem is I want to have more control on some of the transisitors characteristic such as Width etc.

How do I make the software do it?

now , when lets say I change in one of the places the width of the transistor
Virtuoso changes it for all theb transistors in the design .

another question I have is regarding leakage currents , How Virtuoso deals with this important issue ? Does it ignores it?

 

[erikl]

... more control on some of the transistors characteristic such as Width etc.

You may assign parameters (like w or l ) to your symbol's CDF (see here how it's done). Then you can assign individual values to the instanced symbols. See the C@dence basic (or analogLib) MOSFET symbols how it's done there. Copy it to your lib with a new name, and change it to your requirements.

... regarding leakage currents , How Virtuoso deals with this important issue ? Does it ignores it?

Of course not. For simulation purpose, each symbol has a spectre (or spice, eldo, ...) equivalent view, which points to the appropriate simulator model. This model contains the (w- & l-dependent) leakage current Is.

 

[yans123]

Thanks ,

How do I measure the leakage currents ?
( subthreshold , reverse bias pn diddes etc. )

I use the models from PTM .

Thanks ...

 

[erikl]

How do I measure the leakage currents ?

Depends on your simulator. Read the user guide.

 

[yans123]

Thanks again for your answers...

I use spectre simulation with spice model files from PTM.
I didn't find any user guide with explanations on how to that ?
What kind of simulation should I do ?
Where to put the probes to find out the different leakage currents?

some more questions :
8-O
I created CMOS inverter with this cells and I put ,few inverters in my design.
I want this inverter to be different from one another ( different transistors width)
but when I apply changes to one instance it changes all the instances .
how to apply changes only to occurrence of cell I created ?


thanks ...

 

[erikl]

I use spectre simulation with spice model files from PTM.
I didn't find any user guide with explanations on how to that ?

If you have the spectre tool, you should also have its user guide. And spectre has a good on line help function. Use
spectre -h ...

What kind of simulation should I do ?
Where to put the probes to find out the different leakage currents?

A DC simulation. Spectre will save the OP's of all devices with all parameters, including the leakage currents. You don't need to put probes.

I created CMOS inverter with this cells and I put ,few inverters in my design.
I want this inverter to be different from one another ( different transistors width)
but when I apply changes to one instance it changes all the instances .
how to apply changes only to occurrence of cell I created ?

I've answered this already in my first posting above.