hierarchy design in IC Compiler

[ldhung]

Hello,
I am designing a chip with a TOP level chip and many instances inside.
I synthesized and converted the sub designs to CEL layout by IC Compiler.
Now I want to place and route a TOP level which contains those sub designs in hierarchy design.
I included layout sub designs in reference_library and link_library, but when I run place command, the whole design are flattened and encountered error.
How to solve this problems ?
Thanks in advance.

 

[pavanks]

If they are big blocks u can manually place them and do the top level routing.

 

[ldhung]

I did, but the ICC informed that the cells are misplaced or placed nor correct.