Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help with ASIC projects

Status
Not open for further replies.

bobjee

Newbie level 5
Joined
Jun 2, 2009
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
asic projects

Hi All,

I need to design a project spec for a course. The course needs a design project which requires verilog. The verilog code is to be synthesized using cadence. Can some one suggest me good projects or some ideas on which I can design the spec on.

Thank you
 

bobjee

Newbie level 5
Joined
Jun 2, 2009
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
asic projects

Hi,

The project must be a course project. It must take 8 to 10 weeks to complete the project.

It would be great if the project idea can be useful for real time applications.

Thank you
 

pgbackup

Newbie level 6
Joined
May 7, 2009
Messages
13
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,283
Activity points
1,607
asic projects ideas

Check out opencores.org. Many of the cores there are synthesizable.

A good project might be a ALU supporting IEEE-754 adder/sub, mult, div
 

bobjee

Newbie level 5
Joined
Jun 2, 2009
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
Hi,

I have checked opencores.org. I have found some interesting projects over there. But I don't think they can be used as a course project. Can some one help me out with few more ideas.

Thank you
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top