Help with ASIC projects

[bobjee]

asic projects

Hi All,

I need to design a project spec for a course. The course needs a design project which requires verilog. The verilog code is to be synthesized using cadence. Can some one suggest me good projects or some ideas on which I can design the spec on.

Thank you

 

[ljxpjpjljx]

asic+projects

how much size does your design need?

 

[bobjee]

asic projects

Hi,

The project must be a course project. It must take 8 to 10 weeks to complete the project.

It would be great if the project idea can be useful for real time applications.

Thank you

 

[pgbackup]

asic projects ideas

Check out opencores.org. Many of the cores there are synthesizable.

A good project might be a ALU supporting IEEE-754 adder/sub, mult, div

 

[bobjee]

Hi,

I have checked opencores.org. I have found some interesting projects over there. But I don't think they can be used as a course project. Can some one help me out with few more ideas.

Thank you