stuntmaster
Newbie level 4
i am new to verilog and i need to get 160Hz form my clock oscillator which is
25.17Mhz using verilog i tried with this code
always @(posedge clk25mhz)
begin : process_2
if (count2 < 160)
begin
count2 <= count2 + 1;
end
else
begin
count2 <= 0;
end
if (count2 < 80)
begin
clk_160hz <= 1'b 0;
end
else
begin
clk_160hz <= 1'b 1;
end
end
25.17Mhz using verilog i tried with this code
always @(posedge clk25mhz)
begin : process_2
if (count2 < 160)
begin
count2 <= count2 + 1;
end
else
begin
count2 <= 0;
end
if (count2 < 80)
begin
clk_160hz <= 1'b 0;
end
else
begin
clk_160hz <= 1'b 1;
end
end