Help Plz about freq divison

[stuntmaster]

i am new to verilog and i need to get 160Hz form my clock oscillator which is
25.17Mhz using verilog i tried with this code


always @(posedge clk25mhz)
begin : process_2
if (count2 < 160)
begin
count2 <= count2 + 1;
end
else
begin
count2 <= 0;
end
if (count2 < 80)
begin
clk_160hz <= 1'b 0;
end
else
begin
clk_160hz <= 1'b 1;
end
end

 

[ckaa]

In your code you are assuming that your 25MHz reference clk has a time period of 1 second. So you assume that if your counter counts to 80 and inverts the polarity of your clk160hz signal you get 80Hz and invert again at count = 160 and that gives you 160Hz which is incorrect.
Your clk25mhz has a time period of 40ns and not 1s. You want a 160Hz clock with a time period of 6.25ms. You'll probably need a PLL which divides down your frequency from 25MHz to 160Hz and takes care of your phase (if that's important to you).
If this code is aimed towards a FPGA you can use one of the PLL ips available with your vendor. If not you could search this forum and you'll see lots of posts talking about implementing a PLL in verilog.
Your current code will give you a clock with frequency = 155.27MHz.

 

[stuntmaster]

thx for ur reply do u have any idea how to make this code generates 160Hz form 25.17MHz

 

[RBB]

160Hz is not an integer multiple of 25.17MHz, so you won't be able to directly divide the 25.17MHz clock down. You'll need some sort of PLL, like ckaa suggested.