Help me with One Timing Loop code

[nemolee]

Timing Loop

Now I have one timing loop issue in my design. The code is as follow:

assign dck = scan_tst ? scan_dck :
pg_en ? osc_dck :
en1ch ? lvds_dck_div2 : lvds_dck;

always @(posedge dck or negedge rst_n)
begin
if (!rst_n)
en1ch <= #1 1'b0;
else if (i2c_func_en)
en1ch <= #1 data;
end

How can I fix this issue? Thank you very much.

 

[eda_wiz]

Re: Timing Loop

Now I have one timing loop issue in my design. The code is as follow:

I didnt understand your issue . Could you expalin your issue in detail .. may be I can help..

 

[spauls]

Re: Timing Loop

use "report_timing -loops" option and put these loop in group_path , DC will autoamtically resolve the loop

 

[nand_gates]

Re: Timing Loop

I got ur problem....
And the soln is don't register data use it directly as follows to select dck!

assign dck = scan_tst ? scan_dck :
                   pg_en ? osc_dck :
                   (rst_n & i2c_func_en & data) ? lvds_dck_div2 : lvds_dck;

 

[zhustudio]

Timing Loop

en1ch is an input of dck and dck trig the en1ch. it is timing loop