Re: help me with a concept of using FPGA to verify ASIC Desi
Hi,
Verifying the SOC Rtl using FPGA is very fast as compared to simulation. And it gives more test coverage also. Some simulation can take days to complete whereas it can be done in FPGA in minutes.
In this particular case, I think putting the ARM9 and the module under test in a single FPGA will be very efficient. Ofcourse, this will necessitate to use a lot of resources, like board with high density FPGA, ARM debugger tool etc.
As far as changing the original RTL to make it work for FPGA is concerned, it doesn't take much efforts. Only memory replacement and clock-resets have to taken care.
Regards.