Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
1.Test slave communication, you need a softwave to create a data format.
*Deliver a "address" data format, and to measure sda waveform.
*If you can measure a "ack" on sda, you can program your slave device.
*If you can't measure a "ack" on sda, first try address 00,
second try pull high resister
2.If you want to do other purpose, please that me know, I hope I can help you.
Hi mpig
Actually am doing using veriloga models in cadence, for that initially i require the state machine just for slave part. 1) just it has to read its address,
2) it has to read the data from the bus
3) it has to place the data on the bus
4) start and stop detect
5) it has to send ack
if you have state machine and related schematics for this plz send me yar
plz help me yar
I have done a project in vhdl on the master cpntroller for spartan3.
Wanna share ur slave part of the project ??
If yes, plz mail me
adi31187[at]gmail[dot]com
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
