Genvar:Shift Register

[woeichee]

I would like to implement a set of 32bit shift register using genvar. However, i wonder why the input and output of my block is always 1 bit only instead of 32.

module shift_reg1 #(parameter LENGTH = 3)
( input clk,
input [31:0] in,
output [31:0] out);

wire [63:0] sig;

genvar n;
generate
for (n=0; n<LENGTH; n=n+1)
begin: shift_reg_gen
case
0: dffn1 u1 (
.q(sig[((n+1)*32)-1:n]), .clk(clk), .d(in)
);

LENGTH-1: dffn u1 (
.q(out), .clk(clk), .d(sig[((n-1)*32)+31(n-1)*32)])
);

default: dffn u1 (
q(sig[(n*32)+31n*32)]), .clk(clk), .d(sig[((n-1)*32)+31(n-1)*32)])
);

endcase
end
endgenerate

endmodule


module dffn1( input clk,
input [31:0] d,
output reg[31:0] q);

always @ (posedge clk)
q <= d;

endmodule

Thanks