# Parameterized register chain in Systemverilog

#### shaiko

Hello,

I want to generate a parameterized register chain in Systemverilog.
The goal is to have both the width and depth of the chain to be overridable compile time parameters.
I aslo want the register chain to have an asynchronus reset - and the "default_value" to also be a parameter.

Is the code below correct ?
How should I define "default_value" , "number_of_regs" , "width_reg" ?

Code:
module register_chain
#(
// default_value //
// number_of_regs //
// width_reg //
)
(
input arst ,
input clock ,
input [width_reg-1:0] in_data ,

output logic [0:number_of_regs-1] [width_reg-1:0] out_data
)

assign out_data [ 0 ] = in_data ;

always @ ( posedge clock or posedge arst )
begin
if ( arst == 1'b0 )
out_data = default_value ;
else
for ( integer index = 0 ; index < number_of_regs - 1 ; index ++ )
out_data [ index + 1 ] <= out_data [ index ] ;
end

##### Super Moderator
Staff member
Try something like this
Code:
parameter width_reg = 8,
parameter number_of_regs = 4,
parameter [width_reg*number_of_regs-1:0] default_value = {width_reg*number_of_regs{1'b0}}
There may be a syntax error in there somewhere as I can't check the code.

The instantiation will require you input the default value as a width_reg*number_of_regs vector which can be assigned to the packed array. I usually use something like
Code:
.default_value ({8'h00, 8'h01, 8'h02, 8'h03})
I think the [0] array position will be in the most significant width_reg-bits of the default_value if I'm not mistaken, i.e 8'h00 in the example.

- - - Updated - - -

BTW, that is one of the big differences between packed and unpacked arrays. You can assign some arbitrary vector to a packed array and it will be right justified. You can only assign individual entries in your array when it is a unpacked array, trying to assign something to the entire unpacked array is illegal and will result in an error.

shaiko

### shaiko

points: 2

#### shaiko

Code:
parameter [width_reg*number_of_regs-1:0] default_value = {width_reg*number_of_regs{1'b0}}
I see that you flatten "default_value" from 2d to 1d...why ?
Can't you treat "default_value" as a 2d array when declaring the parameter ?

##### Super Moderator
Staff member
I think I tried using a 2d for the parameter and it didn't work correctly (I don't remember exactly what was wrong, but I think the problem had to do with the instantiation of the module...it could have also been related to VHDL/Verilog).

The packed array structure is merely a different way of representing a 1d when it comes to assigning stuff, so making the parameter 1d can be assigned without issue to the 2d packed array.

I've experimented with both simulations and Vendor synthesis tools in this particular area as I parameterize almost everything I write. The last time I messed around to see the current support for some of this stuff was about 3 years ago, so things might have changed since then.

I suggest just writing a small testcase and see if the tools you use will support it. I try to only use what all tools will support as we regularly have to migrate between different vendors tools.

shaiko

points: 2

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