Verilog/SV: Using an array as a set of individual registers and not RAM

[pbernardi]

Hello,
I would like to have a parameterizable array (let us say, for N in range of 32 to 128 elements), with a high number of parallel R/W access (up to 8 accesses, also parameterizable).

So, when I define the register:

reg [REGSIZE-1:0] g [0:N-1];

it try to infers a distributed RAM, which is not good because 8x parallel accesses to a distributed RAM generate a huge logic. I need the synthesis tool to generate an array of N single registers instead of a distributed RAM. Is this possible?

Alternatively, is it possible to use a generate or other king of loop/parallel processing to a) generate and b) access a set of N individual registers?

 

[FvM]

So, when I define the register:

reg [REGSIZE-1:0] g [0:N-1];

it try to infers a distributed RAM

I don't believe so. In case of doubt, a synthesis tool will implement the solution with smallest overall resource utilisation. If you prefer a specific implementation, it can be enforced by synthesis attributes (if the implementation is feasible).

 

[pbernardi]

Thanks FvM.
The distributed RAM really does not appear in the synthesis report. I will double check why I have that extra amount of logic, must be something else related.

 

[ILIA KALISTRU]

You can generate multiport memory with generate loop, but it will be implemented with registers (FFs). Might work for small memories, but it becomes impractical with any significant amount of memory configured.

For muliport memory of significant sizes you need a much more complicated design. Here a list of some multi-port designs: http://fpgacpu.ca/multiport/