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gate-level netlist simulation problem

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trai

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gate level simulation post

HI

I want to do gate-level simulation for the synthesised netlist without annotating

the sdf file. I just want to verify the function of the netlist not timing.

I use ncverilog to simulate the netlist with the following command:

ncverilog mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero

tsmc18.v is the library cell simulation model
RA1SHD_1024x32 is the memory simulation model

However the simulation result is completely wrong. I dont know what the problem is .

Then I use vcs instead. The command are followed:

vcs mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero

The result is different from the ncverilog case. The behavior of the netlist seems correct but the behavior of the memory failed. For example, the memory access unit in the netlist successfully generates memory control signals to the RA1SHD_1024x32 during simulation. However the memory simulation model doesnt give correct respons to the signals.

Could anyone tell me what was going wrong? Thank you for your reply~
 

ljxpjpjljx

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netlist simulation

maybe your memory lib have some timing check!
 

trai

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gate level simulation issues

There are timing checks in the memory simulation model.

I have turn off the timing check using "+notimingcheck" option.

The timing checks should have no influnce on the momory and cell behavior.

But.... I still not got the expected result.

Added after 56 seconds:


There are timing checks in the memory simulation model.

I have turn off the timing check using "+notimingcheck" option.

The timing checks should have no influnce on the momory and cell behavior.

But.... I still not got the expected result.
 

shalom

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gate level simulation issues

TSMC libraries cannot be simulated with zero delay mode.

Shalom
 

trai

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specify netlist in vcs

Thanks for your reply.

Is there any way to perform functional verfication for the netlist?
 

vlsidft21

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ncverilog nospecify

can you try using +nospecify alongwith +notimingcheck with the ncverilog or vcs command that you have used. If the lib is having specify blocks, they can de-activated with this switch.
 

shalom

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nospecify ncverilog

vlsidft21 said:
can you try using +nospecify alongwith +notimingcheck with the ncverilog or vcs command that you have used. If the lib is having specify blocks, they can de-activated with this switch.
That won't help. TSMC libraries won't work without delays. If anything, unit delay has more chance to work than zero delay.

Shalom
 

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