trai
Newbie level 6
gate level simulation post
HI
I want to do gate-level simulation for the synthesised netlist without annotating
the sdf file. I just want to verify the function of the netlist not timing.
I use ncverilog to simulate the netlist with the following command:
ncverilog mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero
tsmc18.v is the library cell simulation model
RA1SHD_1024x32 is the memory simulation model
However the simulation result is completely wrong. I dont know what the problem is .
Then I use vcs instead. The command are followed:
vcs mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero
The result is different from the ncverilog case. The behavior of the netlist seems correct but the behavior of the memory failed. For example, the memory access unit in the netlist successfully generates memory control signals to the RA1SHD_1024x32 during simulation. However the memory simulation model doesnt give correct respons to the signals.
Could anyone tell me what was going wrong? Thank you for your reply~
HI
I want to do gate-level simulation for the synthesised netlist without annotating
the sdf file. I just want to verify the function of the netlist not timing.
I use ncverilog to simulate the netlist with the following command:
ncverilog mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero
tsmc18.v is the library cell simulation model
RA1SHD_1024x32 is the memory simulation model
However the simulation result is completely wrong. I dont know what the problem is .
Then I use vcs instead. The command are followed:
vcs mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero
The result is different from the ncverilog case. The behavior of the netlist seems correct but the behavior of the memory failed. For example, the memory access unit in the netlist successfully generates memory control signals to the RA1SHD_1024x32 during simulation. However the memory simulation model doesnt give correct respons to the signals.
Could anyone tell me what was going wrong? Thank you for your reply~