AlienCircuits
Member level 5
I am on the path of designing my first SMPS from scratch, and I have found that deviating from 50% duty cycle requires me to have faster switches (ft, bandwidth, whatever you want to describe their switching performance with). I have a suspicion about duty cycle and the maximum switching speed of my transistor, and I am wondering if anyone else already has the answer or if they at least agree or disagree with me.
I'll make a hypothetical example, and tell me if you agree or disagree with me. Say I pick a MOSFET with a maximum switching frequency of 100kHz. Now, if I switch it at 100kHz and try to deviate its duty cycle either below or above 50%, the switching signal will be degraded because for one half of the period, I will need to switch faster (in a shorter time) than the 10us period. I would not be able to achieve a duty cycle of 10%, for example, without a faster rated switch.
Does anyone have a figure for different duty cycles of PWM in the frequency domain? I know this must have been analyzed a million times be people in the past, and the modulation in PWM seems to imply that there must be some frequency effect. If no one gives me an answer, I will have to work this out myself.
I'll make a hypothetical example, and tell me if you agree or disagree with me. Say I pick a MOSFET with a maximum switching frequency of 100kHz. Now, if I switch it at 100kHz and try to deviate its duty cycle either below or above 50%, the switching signal will be degraded because for one half of the period, I will need to switch faster (in a shorter time) than the 10us period. I would not be able to achieve a duty cycle of 10%, for example, without a faster rated switch.
Does anyone have a figure for different duty cycles of PWM in the frequency domain? I know this must have been analyzed a million times be people in the past, and the modulation in PWM seems to imply that there must be some frequency effect. If no one gives me an answer, I will have to work this out myself.
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