Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Limits of duty cycle for ICM7555 IC?

Not open for further replies.
Do you know what the max duty cycle can be of the output at 120kHz?
--- Updated ---

Just noticed the graph, Fig 12, on page 10 of the ICM7555 datasheet is gives RA=RB=1k and C=7nF giving 200kHz....whereas the equation (1) on page 12 gives that as 65.7kHz.
--- Updated ---

Basically, we need the following 555 based sync’ing cct to be able to deliver pulses of <500ns width at 240kHz. So the 555 output must be 240kHz, with a duty cycle of no less than 0.91. Do you think this is possible with a ICM7555?

LTspice and jpeg attached of sync’ing cct (it syncs a UCC28070A)


  • 555 cct.jpg
    555 cct.jpg
    117.5 KB · Views: 64
    1.1 KB · Views: 50
Last edited:

Try applying a variable voltage to pin 5 (Ctl). The greater the voltage, the greater the duty cycle.
This assumes the 7555 works the same as 555 IC.
As far as I can tell, a certain amount of current must flow out of pin 5. Therefore your control voltage must sink rather than source current.
You can do extreme duty cycles either way (on time or off time) with diode(s) parallel to timing resistor, xyz-prefix 555 pwm-ing via control pin is - as far as I remember - limited to pretty much same as why it has a 5-5-5k divider inside: 1/3rd to 2/3rds vcc fiddling range. Do check for yourself, just in case.

If you have that as a tht IC, ffs man, put it on a breadboard and see when Vout becomes an unacceptable sludge of a signal or of woeful amplitude for triggering ffs and logic downstream with an oscilloscope and a trimpot on pin 5. NXP's test set-up isn't what you'll do with it, after all.

I think 555 fmax should be interpreted similar to OA or any other device's fmax (much less than might be hoped for from what top of a datasheet claims, and depends on circuit used in, etc.).
Youre right i should breadboard it...but i think it'll be quicker at this point to re-lay the board as the attached.
I am moving into a lab unit soon, to put this all together, and i have to order all the kit etc, so i wont have time to build a breadboard of it now....getting a new PCB from China will be cheap.

Any improvement on the attached well appreciated......i am pretty sure that ICM7555 wont be able to do much less than 1us output pulse width......i need <500ns for the UCC28070A sync pulses (my fsw is 60khz for each booster)


  • 400ns pulse trains.jpg
    400ns pulse trains.jpg
    114.3 KB · Views: 58
  • 400ns pulse
    1.5 KB · Views: 46
Thanks, its tempting to stick to the 555, but i think the version with post-buffers is the one now....but i may exchange the buffers for sot23-5 gate drive IC's, as the buffers only come in SOIC16.

The attached is the finished version of 400ns pulse trains...any improvements greatly appreciated...


  • 400ns pulse trains with fet drivers.jpg
    400ns pulse trains with fet drivers.jpg
    131.5 KB · Views: 56
  • 555_fet
    1.6 KB · Views: 42

...Actually no, the gate driver input is not schmitt trigger protected, so there is a danger of double such, the attached is the finished version.....any improvements greatly appreciated


  • 400ns pulse trains with monostables.jpg
    400ns pulse trains with monostables.jpg
    125.6 KB · Views: 54
    1.4 KB · Views: 37

Thankyou very much...that UC3856 is a very impressive chip!

If we used it, we could get rid of the 555, and also loose the CD74HC123...and just keep the D type and the NORS.....we could use two of our "spare" NORs (to make an OR) to take an input from each output of the UC3856, to give us the overall 240kHz square wave with 400ns dead time......which then gets fed to the Dtype--->NORs.

...Or we could use the UC3856 to produce the two antiphase pulse trains...and just use the CD74HC123 to cut them down to 400ns pulses.
Matter of fact, we could use a cheaper half bridge driver to produce the two anti-phase pulse trains...EG LM5030

..scrub that, its 0.5mm pitch....but an ICE2HS01G could produce the two anti-phase pulse trains.....we would just need to somewhow disable its overload shutdown feature, so it keeps pulsing, even though its opto feedback pin is effectively reporting overload...

...Do you agree, putting 1V into ICE2HS01G LOAD pin will keep it pulsing its outputs?
Woops, cant use ICE2HS01G as Vin(start) is 12.7V, and we only have 12v, and no room for a booster.
--- Updated ---

UCC38084/6 sounds really good too.
Any cheaper half bridge drivers in SOIC much appreciated. (Vin<12V).

Last edited:

Do you think the slope compensation resistor of UCC38084 can be sized to cut the duty cycle to say 25% when its free running as just an anti-phase pulse train oscillator?...seems counter intuitive but it must be so?

SG3525 , at 33p, sound slike the king of free running anti phase pulse trains

..presumbaly just set it up in voltage mode and let it fly.

Not open for further replies.

Part and Inventory Search

Welcome to