frequency divider (430Mhz to 10Mhz)

[navyashree]

what would the verilog code to be change a 430Mhz clock to 10Mhz with a reset input

 

[shaiko]

In general - you should use a PLL for such a division ratio . Instead of trying to divide it with logic.

 

[KlausST]

Hi,

Count from 0 to 42, then start with 0 again...

Klaus

- - - Updated - - -

Hi,

In general - you should use a PLL for such a division ratio . Instead of trying to divide it with logic.

This is true, especially when you want to drive clocked gates with the 10MHz.

Klaus

 

[Warpspeed]

Usual way for a PLL would be a dual modulus prescaler such as divide by 10/11 used with a fixed divide by four. That would provide division ratios from 40 to 44.
A VCO on the output would then remove the jitter.

But this would have to be be a constantly running frequency divider, not a resettable static counter which is a very different thing.

 

[dpaul]

Relax Guys,
This is another homework type of Q, where the OP wants the Verilog code!
Let her figure out the code, it is not difficult.

 

[Thoma HAUC]

Hi navyashree,


I found for several years a perl script at the following link :
https://fractional-divider.tripod.com/

Hope this help.

Thoma