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for loop synthesizable r not in verilog?

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sadhula_swetha

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for loop is synthesizable or not?
if synthesizable means what is the hardware implemented 4 for loop and all other loops[while,do-while..]
 

FvM

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It's synthesizable and often used to describe parallel structures. Nevertheless it's purpose is often misunderstood by beginners, who expect a for loop to create a sequence in time.
 

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