for loop synthesizable r not in verilog?

[sadhula_swetha]

for loop is synthesizable or not?
if synthesizable means what is the hardware implemented 4 for loop and all other loops[while,do-while..]

 

[FvM]

It's synthesizable and often used to describe parallel structures. Nevertheless it's purpose is often misunderstood by beginners, who expect a for loop to create a sequence in time.