If the write clock is 100MHz and the read clock is 200MHz, and if the data is coming on every clock cycle in the write domain, would I need a FIFO? If the FIFO is required what would be the depth of it? If the FIFO is not required, how would I transfer the data from write clock to read clock?
In other words, you can't continuously read data. By using a FIFO, you can read data at 200 MHz for a limited time, if the FIFO has been filled before. This is a question about your application requirements, that haven't been mentioned yet.