Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] FIFO Depth calculation for an async FIFO

Status
Not open for further replies.
F

fragnen

Full Member level 3
Joined
Apr 3, 2019
Messages
182
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,299
Data is written as 80 data per 100 clock cycles to a FIFO and being read at 4 data per 10 clock cycles. The write and read clock of the FIFO is running at 100 MHz and 200 MHz respectively and this write and read clock are asynchronous to each other. What will be the depth of this FIFO.

In this case, the depth of 32 should be sufficient if this FIFO was a synchronous FIFO if the write and read clock was synchronous to each other. But since write and read clock are asynchronous to each other, the FIFO will be an asynchronous FIFO and the depth of 32 will not work. Please provide a proper depth of this asynchronous FIFO.
 

Solution
ads-ee
Unless the two clock are derived from the same source clock there is no possible depth that will work with a sustained transfer. Clocks derived from different sources won't ever be exactly the same frequency and that difference will cause an asynchronous FIFO to eventually overflow or underflow as the actual ingress and egress rates are not identical.

If the two clocks are derived from the same source clock then barry's observation is valid and I would add additional depth to match the amount of CDC that is used to transfer the address pointers and flags.
Sort by date Sort by votes
I'm confused. Your input data rate is 80M-samples/sec, same as your output data rate. Unless you've got some big latency between write and read that you're not telling us about, where's the problem?
 

Upvote 0 Downvote
Unless the two clock are derived from the same source clock there is no possible depth that will work with a sustained transfer. Clocks derived from different sources won't ever be exactly the same frequency and that difference will cause an asynchronous FIFO to eventually overflow or underflow as the actual ingress and egress rates are not identical.

If the two clocks are derived from the same source clock then barry's observation is valid and I would add additional depth to match the amount of CDC that is used to transfer the address pointers and flags.
 

Upvote 0 Downvote
Solution
The two clocks are asynchronous to each other.

The write clock is running at 100 MHz. The read clock is running at 200 MHz. Data is coming at the Data input pin of the asynchronous FIFO at a rate of 80 data per 100 write clock cycles. Data is read from the asynchronous FIFO at a rate of 4 data per 10 read clock cycles.
--- Updated ---

ads-ee said:
If the two clocks are derived from the same source clock then barry's observation is valid and I would add additional depth to match the amount of CDC that is used to transfer the address pointers and flags.
Click to expand...
How much will be the additional depth?
 

Upvote 0 Downvote
fragnen said:
The two clocks are asynchronous to each other.

The write clock is running at 100 MHz. The read clock is running at 200 MHz. Data is coming at the Data input pin of the asynchronous FIFO at a rate of 80 data per 100 write clock cycles. Data is read from the asynchronous FIFO at a rate of 4 data per 10 read clock cycles.
--- Updated ---


How much will be the additional depth?
Click to expand...
You just repeated yourself while completely ignoring what people are telling you. To summarize:
1) If the two clocks are synchronous then your FIFO only needs to be deep enough to accommodate latency.
2) If the two clocks are asynchronous you will eventually overrun or underrun the FIFO, no matter how big it is.
 

Upvote 0 Downvote
barry said:
You just repeated yourself while completely ignoring what people are telling you. To summarize:
1) If the two clocks are synchronous then your FIFO only needs to be deep enough to accommodate latency.
Click to expand...
How to calculate such depth to accommodate latency and how much will be the depth? Which latency are you referring?
 

Upvote 0 Downvote
@barry,
"You just repeated yourself while completely ignoring what people are telling you. To summarize:"
Because this is a question from fragnen!

Dear members,
please consider these previous posts from the OP while trying to answer this question/thread-


I did not compare in depth the above previous posts from fragnen to this post, but I have a feeling that the same question is being asked.
 

Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top