External input & output delay attributes in RC

[nikhilindia85]

wat does external input &output delay attributes in RC.wat it refers

 

[rameshsuthapalli]

synthesys

Hi all,

The input/output delay that u have specified is used for caluculating the Input-clock/clock-output timing caliculations.

regards,
ramesh.s

 

[shiv_emf]

synthesys

as system which u design has to work with other peripherals whr in u require meet some criteria .. data going out of module shud be out before certain time..

data coming into module is having certain delay ..so using external input & output delay used to further constrain our design !!!!!!

Shiv

 

[vlsichipdesigner]

Re: synthesys

To better understand the concepts go over these links

https://www.vlsichipdesign.com/static timing analysis

 

[shiv_emf]

synthesys

above site is nt constructed properly !!!!!!!!!!

 

[vlsichipdesigner]

Re: synthesys

Request you to be bit elaborate, in what sense the website is not constructed properly.