dhaval4987
Full Member level 3

Hey all,
I synthesized a verilog file using Design Compiler.
Now I am using that same file in Nanotime and WhenI try to link the design, it says,
ERROR: NetComp: 0x3024008: cannot fine subcircuit definition or function model not for instance v2e_205.
but my question is: I dont have any instance named v2e_205 in my verilog. Also the structure of the synthesized looks errorfree and the frmat is correct.
why is this v2e_205 is coming! from where!?
I synthesized a verilog file using Design Compiler.
Now I am using that same file in Nanotime and WhenI try to link the design, it says,
ERROR: NetComp: 0x3024008: cannot fine subcircuit definition or function model not for instance v2e_205.
but my question is: I dont have any instance named v2e_205 in my verilog. Also the structure of the synthesized looks errorfree and the frmat is correct.
why is this v2e_205 is coming! from where!?