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Error while compiling Synthesized Verilog file

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dhaval4987

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Hey all,

I synthesized a verilog file using Design Compiler.

Now I am using that same file in Nanotime and WhenI try to link the design, it says,

ERROR: NetComp: 0x3024008: cannot fine subcircuit definition or function model not for instance v2e_205.

but my question is: I dont have any instance named v2e_205 in my verilog. Also the structure of the synthesized looks errorfree and the frmat is correct.

why is this v2e_205 is coming! from where!?
 

permute

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is there an instance named v2e? it sounds like something that is either autogenerated or in a generate statement. the error also seems to be trying to find the function "not". It's possible this was in some library or defined in some other file. Verilog synthesis has often worked by concatenating files together, in which case it is possible that removing or changing a module that had `define or `include statements can cause the build to fail.
 

dhaval4987

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there is not instance named v2e. so how exactly should I proceed?

---------- Post added at 04:11 ---------- Previous post was at 04:10 ----------

and as far as 'not' is concerned, isnt it predefined in verilog?

---------- Post added at 04:17 ---------- Previous post was at 04:11 ----------

I resynthesized and now it is showing the exact same error but instead of v2e_205, it says v2e_26.

I dont know how to deal with this.
 

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