I'm using dc_shell to the logical sinthesis and when the tool began the mapping optimization sometimes occurres this error:
Code:
Beginning Mapping Optimizations (Medium effort)
-------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:15 1390979.4 5455.49 3674589.0 2499849.8
0:00:15 1390979.4 5455.49 3674589.0 2499849.8
0:00:16 1521130.8 4366.23 3491686.0 1534308.2
0:00:16 1586206.4 4366.23 3491423.2 1532532.5
0:00:16 1644827.6 4366.23 3491391.2 1532197.8
0:00:17 1847733.9 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
Abort at 951
The tool has just encountered a fatal error:
If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at http://solvnet.synopsys.com/EnterACall.
* For information about the latest software releases, go to the Synopsys
SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.
* For information about required Operating System patches, go to
http://www.synopsys.com/support
Fatal: Internal system error, cannot recover.
Release = 'F-2011.09-SP5' Architecture = 'linux' Program = 'dc_shell'
Exec = '/synopsys/syn/linux/syn/bin/common_shell_exec'
'268739091 268740970 268865003 269112253 179019362 179093888 179160654 179206411 179215724 179266890 159953125 159953934 160323728 159163877 159181273 159200901 154756209 153674072 267933445 268080645 270598122 270604202 270605040 267986999 268034391 268080645 270598122 270604202 270763266 270784645 270608231 270810241 268075051 146660181 146641693 147359449 147344077 147366974 147138141 146321393 146308403 149922693 134670779 134656066 3374310'
I've tryed to reinstall and install other versions but the problem still occurs.
What disgust me is that the error does not occur all the time.
Someone knows something to help me?
Have you tried to synthesis using different designs (adder, counter) with relax timing constraints and see if the tool still give the same error? If it is, then you should contact the vendor.
As you suggested, i tried to synthesis two different designs, actually, i used some designs that were instantiated in the main design who are giving the error.
Both, 32-bits adder and Latch D, didn't give the error. The tool works fine, and give me all the reports, area, timing and power.
I noticed that in main design there is a message reporting:
Code:
Information: There are 1317 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Runing the check_design the tool just show that there are some signals who are binary constants, and some repeated signs in some instantiation (that are correct).
So, a friend mine made a synthesis for a floating point unit 32 bits single precision on it. Using SV. But the code generated by the tool, with the mapped code, it is in verilog.
But he is not an undergraduate student anymore, and it is a little complicated to talk with him, so i'm using the forum to get help.
Try to search:
Modeling with SystemVerilog in a Synopsys Synthesis Design Flow Using Leda, VCS, Design Compiler and Formality, by Stuart Sutherland (2006).
or
The Benefits of SystemVerilog for*ASIC Design and Verification, by Synopsys (2007).
--//--
Yesterday, i tried to delete some commands from the .src with some sets (posted above), and the tool synthesized one design, but not anothers. I'm fighting.
I would suggest to try synthesis the design (the initial top level design that produces the errors) with only "create_clock" constraint and see how to tool behave.
I would suggest to try synthesis the design (the initial top level design that produces the errors) with only "create_clock" constraint and see how to tool behave.
I found a way to the synthesis works, let me explain what did i do:
Remove de command <set hdlin_auto_save_templates "true"> from .scr (i read in somewhere that this setting would not be used in DC version after 2007);
Change the way to read de .sv files from <analyze -f sverilog -lib work ../RTL/<design>.sv> to <read_sverilog {../RTL/<design>.sv}>;
The tool didn't give any error.
But now in the timming report didn't appear the SLACK, just a message: Path is unconstrained.
I know from the other synthesis that the slack is around 3.93 with a clock period of 65, but now making this changes they don't show it anymore.