Error using Design Compiler

[jgnr]

Hello everyone,

I'm using dc_shell to the logical sinthesis and when the tool began the mapping optimization sometimes occurres this error:

  Beginning Mapping Optimizations  (Medium effort)
  -------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:15 1390979.4   5455.49 3674589.0 2499849.8                          
    0:00:15 1390979.4   5455.49 3674589.0 2499849.8                          
    0:00:16 1521130.8   4366.23 3491686.0 1534308.2                          
    0:00:16 1586206.4   4366.23 3491423.2 1532532.5                          
    0:00:16 1644827.6   4366.23 3491391.2 1532197.8                          
    0:00:17 1847733.9      0.00      -0.0       0.0                          
    0:00:21 1849075.3      0.00      -0.0       0.0                          
    0:00:21 1849075.3      0.00      -0.0       0.0                          
    0:00:21 1849075.3      0.00      -0.0       0.0                          
    0:00:21 1849075.3      0.00      -0.0       0.0                          
    0:00:21 1849075.3      0.00      -0.0       0.0                          

Abort at 951


The tool has just encountered a fatal error:

If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at http://solvnet.synopsys.com/EnterACall.

* For information about the latest software releases, go to the Synopsys
  SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.

* For information about required Operating System patches, go to
  http://www.synopsys.com/support


Fatal: Internal system error, cannot recover.

Release = 'F-2011.09-SP5'  Architecture = 'linux'  Program = 'dc_shell'
Exec = '/synopsys/syn/linux/syn/bin/common_shell_exec'

'268739091 268740970 268865003 269112253 179019362 179093888 179160654 179206411 179215724 179266890 159953125 159953934 160323728 159163877 159181273 159200901 154756209 153674072 267933445 268080645 270598122 270604202 270605040 267986999 268034391 268080645 270598122 270604202 270763266 270784645 270608231 270810241 268075051 146660181 146641693 147359449 147344077 147366974 147138141 146321393 146308403 149922693 134670779 134656066 3374310'

I've tryed to reinstall and install other versions but the problem still occurs.
What disgust me is that the error does not occur all the time.
Someone knows something to help me?

 

[soloktanjung]

Looking at the WNS/TNS does not make sense to me.

Beginning Mapping Optimizations (Medium effort)
-------------------------------

ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:15 1390979.4 5455.49 3674589.0 2499849.8
0:00:15 1390979.4 5455.49 3674589.0 2499849.8
0:00:16 1521130.8 4366.23 3491686.0 1534308.2
0:00:16 1586206.4 4366.23 3491423.2 1532532.5
0:00:16 1644827.6 4366.23 3491391.2 1532197.8
0:00:17 1847733.9 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0
0:00:21 1849075.3 0.00 -0.0 0.0

Have you tried to synthesis using different designs (adder, counter) with relax timing constraints and see if the tool still give the same error? If it is, then you should contact the vendor.

Thanks.

 

[jgnr]

As you suggested, i tried to synthesis two different designs, actually, i used some designs that were instantiated in the main design who are giving the error.

Both, 32-bits adder and Latch D, didn't give the error. The tool works fine, and give me all the reports, area, timing and power.

I noticed that in main design there is a message reporting:

Information: There are 1317 potential problems in your design. Please run 'check_design' for more information. (LINT-99)

Runing the check_design the tool just show that there are some signals who are binary constants, and some repeated signs in some instantiation (that are correct).

The constants i mean are:

logic H0_0, H0_1, H0_2, H0_3, H0_4, H0_5, H0_6, H0_7, ... , H15_49;

always_comb begin
// Coeficiente H0 0000000000001011 [0]
H0_0 = 1'b1;
H1_0 = 1'b1;
H2_0 = 1'b0;
H3_0 = 1'b1;
H4_0 = 1'b0;
H5_0 = 1'b0;
H6_0 = 1'b0;
H7_0 = 1'b0;
H8_0 = 1'b0;
H9_0 = 1'b0;
H10_0 = 1'b0;
H11_0 = 1'b0;
H12_0 = 1'b0;
H13_0 = 1'b0;
H14_0 = 1'b0;
H15_0 = 1'b0;
// Coeficiente H1 0000000000000110 [1]
.
.
.
end

So 50*15 = 800 + (repeat signs in instantion*, and other signals assign in zero and one);

module_instantiated instantiation_name (a,a,out1,out2);

The warnigs i noticed were that.

The code i'm using to compile on dc_shell is:

set search_path {"."  "../../techlib/xh035/liberty/D_CELL/MOS"}
set symbol_library { D_CELLS.sdb  }
set target_library { D_CELLS_MOS_typ_3_3V_25C.db }
set link_library {* D_CELLS_MOS_typ_3_3V_25C.db dw_foundation.sldb}
set synthetic_library { dw_foundation.sldb }
set verilogout_equation "false"
set verilogout_no_tri "true"
set write_name_nets_same_as_ports "true"
set verilogout_single_bit "false"
set hdlout_internal_busses "true"
set bus_inference_style "\%s\[\%d\]"
set sdfout_no_edge "true"
set fix_multiple_port_nets -all
set hdlin_auto_save_templates "true"
define_design_lib work -path ../work

analyze -f sverilog -lib work ../RTL/<module_1>.sv
analyze -f sverilog -lib work ../RTL/<module_2>.sv
.
.
.
<analyzing all modules in main design>
.
.
.
analyze -f sverilog -lib work ../RTL/<design>.sv



elaborate <design> -lib work

create_clock -period 60 -name clk [find port clk]
set_input_transition -max 2 [get_ports {clk}]
set_input_delay 1 -clock clk [get_ports {X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 reset}]
set_output_delay 1 -clock clk [get_ports {S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0}]
set_load 0.2 [get_ports {*}]
set_wire_load_model -name 0_5k

link

uniquify
current_design <design>
compile

write -format verilog -hier -output ../resultados/<design>.v
write_sdf -version 2.1 -significant_digits 4 "../resultados/ <design>.sdf"
write_sdc "../resultados/<design>.sdc"
report_timing > "../resultados/<design>_timing.rpt"
report_area > "../resultados/<design>_area.rpt"
report_power > "../resultados/<design>_power.rpt"

If this datas may help you to help me would be awesome.

Thanks for helping.

 

[sakthikumaran87]

Hi one basic doubt. Can Synopsys DC synthesis SV codes?? Pl guide.

 

[jgnr]

Hi one basic doubt. Can Synopsys DC synthesis SV codes?? Pl guide.

So, a friend mine made a synthesis for a floating point unit 32 bits single precision on it. Using SV. But the code generated by the tool, with the mapped code, it is in verilog.

But he is not an undergraduate student anymore, and it is a little complicated to talk with him, so i'm using the forum to get help.

Try to search:
Modeling with SystemVerilog in a Synopsys Synthesis Design Flow Using Leda, VCS, Design Compiler and Formality, by Stuart Sutherland (2006).
or
The Benefits of SystemVerilog for*ASIC Design and Verification, by Synopsys (2007).

--//--

Yesterday, i tried to delete some commands from the .src with some sets (posted above), and the tool synthesized one design, but not anothers. I'm fighting.


Thanks for answering.

 

[soloktanjung]

I would suggest to try synthesis the design (the initial top level design that produces the errors) with only "create_clock" constraint and see how to tool behave.

Thanks.

 

[jgnr]

I would suggest to try synthesis the design (the initial top level design that produces the errors) with only "create_clock" constraint and see how to tool behave.

Thanks.

I tried, but didn't work.

I found a way to the synthesis works, let me explain what did i do:

Remove de command <set hdlin_auto_save_templates "true"> from .scr (i read in somewhere that this setting would not be used in DC version after 2007);
Change the way to read de .sv files from <analyze -f sverilog -lib work ../RTL/<design>.sv> to <read_sverilog {../RTL/<design>.sv}>;

The tool didn't give any error.

But now in the timming report didn't appear the SLACK, just a message: Path is unconstrained.

I know from the other synthesis that the slack is around 3.93 with a clock period of 65, but now making this changes they don't show it anymore.

Do you have any idea about how to show it?

Thanks to much hairo.