encounter timing optdesign

[Johnlee0329]

encounter timing optdesign
Hi all,
Do you know how to use encouter optdesign to fix hold violation on in2reg path effectively when do postroute optimization? I have tried many time through modification setoptmode command and setclockdomains command, but it didn't work. It seems that optdesign only fixs hold violations on reg2reg path. when I run optdesign every time, it reports that: setClockDomains fromtype register totype register, no any other path, such as in2reg, reg2out......, is there any other setting for optdesign to fix hold violations on path in2reg? It's urgent.Thanks a lot.

 

[rca]

just take care with in2reg hold time violations, to fix only real violations, some time is better to relax the set_input delay constraints in the sdc, because the tool can add a huge number of buffer to fix unreal violation.

 

[soloktanjung]

Hi rca,

What do you mean by relaxing the set_input_delay? is it by reducing the delay or increasing the delay? can that be applied to set_output_delay also? Because I have problems with reg2out hold time violation. I tried to reduce the clock freq but didnt work.

Thanks in advance.

hairo

 

[rca]

no you need to reduce the set_output_delay. This command define how much time is needed outside the chip., so if you reduce this value, you will provide more time for the path inside the chip.

 

[soloktanjung]

Hi,

I reduced the set_output_delay value from 1.0 ns to 0.5 ns but still there is reg2out hold time violation at post-CTS stage (all reg2out paths, max violation is -0.7 ns). I don't know what else can I do. Do you have any suggestion? The clock period is 4.0 ns.

One more thing, after I run optdesign -postCTS -hold to optimize hold time, it creates setup time violation. So if we solve hold time violation, then we can proceed to route stage (don't cant post-cts setup time)? or we need to solve both hold and setup violation?


Thanks.

 

[rca]

what was the violations before and after?

 

[soloktanjung]

Before was -1.0 ns and after reducing the set_output_delay, hold violation reduced to -0.7 ns.

Thanks.

 

[rca]

If you report the full path detail, you will see where the timing is used, and you could found if the set_output_delay is the responsible or not of your violation....

 

[soloktanjung]

OK thank you. I got it solved after analyzing the full path.

Thanks again.

 

[iwpia50s]

While you can fix input2reg hold violations at the block level, it is better to get the top level timing so you know your violations are real.