Effect of PI and PO Constraints on Test Coverage

[S.Nikhil]

Hi,

Following is the description of a cell used in our design.
module EMPTYCELL(IP);
input IP;
endmodule

The input ports of the design does have a connection to these cells (EMPTYCELL) as described above. Thus, we feel that during ATPG inorder to avoid errors at the DRC stage (IN ATPG Flow) it is necessary to constrain the input ports having connection with this CELL. But by doing so (i.e. add PI constraints input port names using Tetramax), i am getting reduced test coverage.

Can anyone guide me about this.

While doing ATPG, what would be the effect of adding PI and PO constraints on the test coverage.

Thanks

Nikhil

 

[vlsi_eda_guy]

Hi Nikhil,

If the input port is directly and connecting only to this emptycell , then there is no need to constrain the inputs.

If there is some other path as well for the input ports faults to be observed then definitely you will see a reduction in the coverage.

And why do you think that it will lead to some DRC error?


-vlsi_eda_guy