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Doubt in Verilog Synthesis

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surajkashyap

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Hi All,

The delay values given in Verilog statements cannot be synthesized by the tool, I have a doubt in this. The RTL designer would have given delay values to enhance timing and avoid timing failures and to bring about proper synchronization right. If this is not synthesizable, won't it lead to timing violations and design failure ???

Thank you,
Suraj Kashyap
 

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Hi All,

The delay values given in Verilog statements cannot be synthesized by the tool, I have a doubt in this. The RTL designer would have given delay values to enhance timing and avoid timing failures and to bring about proper synchronization right. If this is not synthesizable, won't it lead to timing violations and design failure ???

Thank you,
Suraj Kashyap

Verilog delays are simulation only and are primarily only used for testbenching, synthesis uses a timing constraints file (SDC file) to synthesize to a given timing target.
 

surajkashyap

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Verilog delays are simulation only and are primarily only used for testbenching, synthesis uses a timing constraints file (SDC file) to synthesize to a given timing target.


Hi,

Thank you so much for your reply. Can you elaborate a little more about the SDC file. Should a new SDC file be wriiten for every new design which you do? How to give timing information related to millions of path in todays high density asics
 

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Thank you so much for your reply. Can you elaborate a little more about the SDC file. Should a new SDC file be wriiten for every new design which you do? How to give timing information related to millions of path in todays high density asics
You usually write a new SDC file for each design you do, unless you always name every clock and signal in your designs the same every time.

The SDC file contains the clock(s) constraints and input/output constraints of the design. You don't give millions of paths. Those millions of register to register paths are taken care of by the clock constraint and any constraints dealing with asynchronous/synchronous clocks in the design.

You should just go find a tutorial on writing SDC constraints, oddly enough Altera (FPGA vendor) has written some tutorials on the subject (even though SDC is Synopsys Design Constraints)
quick start tutorial
cookbook
 

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I think the answer is like this... You write a Verilog model for a block which should not have any time delay values. The idea of block is that it should not have any element which are not synthesizable. All the delay values should be used in a separate file to test the block. The tests written should be in a separate file. If you are a newbie most of the books teaching Verilog will have test benches and delay elements in the same file for simplicity but in reality you have to have the block separate.
SDC is mainly needed for timing analysis and PD which is not related the question you asking.
 

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