surajkashyap
Newbie level 6
Hi All,
The delay values given in Verilog statements cannot be synthesized by the tool, I have a doubt in this. The RTL designer would have given delay values to enhance timing and avoid timing failures and to bring about proper synchronization right. If this is not synthesizable, won't it lead to timing violations and design failure ???
Thank you,
Suraj Kashyap
The delay values given in Verilog statements cannot be synthesized by the tool, I have a doubt in this. The RTL designer would have given delay values to enhance timing and avoid timing failures and to bring about proper synchronization right. If this is not synthesizable, won't it lead to timing violations and design failure ???
Thank you,
Suraj Kashyap