wipshami
Member level 1
Hi,
Can I do a timing analysis for the complete top level design including IO with the .libs for IO and spiceNetlist of the MACRO ?
* The top level design is not having any std.cells only MACROs
I am not having .lib models for the MACRO ? are they essential for PT run ? If yes, Can I write out .libs for these MACRO from virtuoso ? (MACRO are designed full custom in virtuoso)
Thanks
Shameel
Can I do a timing analysis for the complete top level design including IO with the .libs for IO and spiceNetlist of the MACRO ?
* The top level design is not having any std.cells only MACROs
I am not having .lib models for the MACRO ? are they essential for PT run ? If yes, Can I write out .libs for these MACRO from virtuoso ? (MACRO are designed full custom in virtuoso)
Thanks
Shameel