Doing timing analysys in PT without .libs

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wipshami

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Hi,

Can I do a timing analysis for the complete top level design including IO with the .libs for IO and spiceNetlist of the MACRO ?

* The top level design is not having any std.cells only MACROs

I am not having .lib models for the MACRO ? are they essential for PT run ? If yes, Can I write out .libs for these MACRO from virtuoso ? (MACRO are designed full custom in virtuoso)

Thanks
Shameel
 

Primetime requires .db (compile .lib file) to work.
Virtuoso could not generate .lib file, you need a characterisation tool for that.
 
Can we do the timing analysis for transistor level custom block in PT after generating .lib using characterisation tool ? Is that the right way ?
or we need to go with tools like nanotime to do transistor level STA ?
 

Yes, with characterization tool you could generate the liberty file from spice netlist (transistor model).
I don't know nanotime.
 

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