Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Sometimes , it is just a warning not the error.
And i remember S1 just use "insert test logic -scan on -test on" to deal with and sometimes you should set the test logic cell. And you can check you training book.
You have instructed the tool to add test logic to resolve S1. In the scan inserted netlist also test logic will be inserted. If you don't constrain the test_en(Test pin), you will again get the S1. Constrain it & run the DFTA in scan inserted netlist.