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Does Encounter RTL Compiler support SystemVerilog ?

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VitalyM4

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Hi!

Does Encounter RTL Compiler support SystemVerilog for synthesis?
Is it feasible to use SV in new projects? It supports well with Cadence tools?
Will I have posibility to do mixed simulations?

Thx
 

VitalyM4 said:
Hi!

Does Encounter RTL Compiler support SystemVerilog for synthesis?
Is it feasible to use SV in new projects? It supports well with Cadence tools?
Will I have posibility to do mixed simulations?

Thx
Click to expand...

Yes, RC supports SystemVerilog for Design. Mixed sim - yes with IUS. Look at www.noveldv.com for SystemVerilog trainings.

Ajeetha, CVC
www.noveldv.com
 

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