swgchlry
Member level 4
snps_clock_gate
When I use synopsys DC to synthesize a design, I want to use the command interface, but I can't understand the parm "arch" of the "elaborate". A example use
'elaborate AAA -arch "BEAVHIOR"', but that example is a VHDL design. Now I use verilog to model a design, how to write the command "elaborate"? Does the content after the -arch is a reserved word? How many values can be assigned? I wrote the command as follows:elaborate AAA -arch "verilog" -update, the compiler show that -update is disabled, why?
When I use synopsys DC to synthesize a design, I want to use the command interface, but I can't understand the parm "arch" of the "elaborate". A example use
'elaborate AAA -arch "BEAVHIOR"', but that example is a VHDL design. Now I use verilog to model a design, how to write the command "elaborate"? Does the content after the -arch is a reserved word? How many values can be assigned? I wrote the command as follows:elaborate AAA -arch "verilog" -update, the compiler show that -update is disabled, why?