Does anyone has some experience of the command "elabora

[swgchlry]

snps_clock_gate

When I use synopsys DC to synthesize a design, I want to use the command interface, but I can't understand the parm "arch" of the "elaborate". A example use
'elaborate AAA -arch "BEAVHIOR"', but that example is a VHDL design. Now I use verilog to model a design, how to write the command "elaborate"? Does the content after the -arch is a reserved word? How many values can be assigned? I wrote the command as follows:elaborate AAA -arch "verilog" -update, the compiler show that -update is disabled, why?

 

[tukken]

script to flatten verilog

This behavior began in version 2001.08 with the introduction of a new
variable, power_cg_flatten. The default value is false; therefore the ungroup
command cannot flatten clock-gating cells. In releases earlier than
version 2001.08, ungroup -all -flatten removes all hierarchy in the design.

Before ungrouping the clock-gating cells, set the following variable:

- dcsh mode (dc_shell)
power_cg_flatten = true

- dctcl mode (dc_shell-t) or psyn_shell mode
power_cg_flatten = true

If the variable is set to true between the elaborate -gate_clock and compile
process, the clock-gating style is integrated and ungroup -all -flatten is done
before compile. Clock-gating cells implemented during elaborate -gated_clock
will lose their attributes. Because of this, compile implements clock-gating
cells that use discrete cells such as latch, or, and and gates. To prevent this
from happening, follow this process:

dc_shell script:

analyze -f verilog top.v
set_clock_gating_style ......
elaborate -gate_clock

ungroup -all -flatten
compile

power_cg_flatten = true

ungroup -all -flatten
write -hier -f verilog -o top_flat.v

In versions earlier than 2001.08, use the following script:

analyze -f verilog top.v
set_clock_gating_style .......

elaborate -gate_clock

clkgate_designs = find (design "SNPS_CLOCK_GATE*")
set_dont_touch clkgate_designs
ungroup -flatten -all

compile

remove_attribute clkgate_designs dont_touch
ungroup -flatten -all

write -hier -f verilog -o top_flat.v

 

[swgchlry]

dc_shell-t set_clock_gating_style

to tukken:
Does it has any relationship to the parm "-architechure"? I haven't got it.

 

[maxsnail]

flatten verilog

I think ARCH is your design is behaviol or rtl or verilog or ...

 

[floatgrass]

snps_clock_gate in synopsys

you can use:
elaborate xxxx -arch "verilog" -lib WORK -update