signal a,b,c,d : ufixed(7 downto 0);
signal temp1 : ufixed(8 downto 0);
signal temp2 : ufixed(8 downto 0);
signal op1, op2 : ufixed(8 downto -1);
temp1 <= a + b;
op1 <= '0' & temp1; --does a divide by 2 implicitly by type declaration
temp2 <= a - b; -- - always increases bit size
op2 <= temp2 & '0';
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