Divider in Megafunction Tools

[fanwel]

Hi all;

I want to write vhdl code for (A+B)/2 algorithm and will implement it in FPGA.
My input is an integer and this algorithm operates continuously with the next stage. For example:
1stage: (3+2)/2=2.5, (3+1)/2=2
2stage: (2.5+2)/2=2.25

The operation requires an integer number and also floating number. My question is which Megafunction tools are better to used: lpm_divider or altfp_div?
Need advise,thank you.

 

[TrickyDicky]

if it is just a divide by 2, or any 2^n, then the lpm divider is not neccessary, as you simply just to a right shift by n. You do not need floating point, the results will be fixed point.

 

[fanwel]

Hi TrickyDicky,

It is mean that I only need a shifter to make the division part? And how to make sure my code is synthesis? Thanks for reply

 

[TrickyDicky]

yes it is only a shift. In VHDL you can write the following code, and it should implement a shift register.

op <= ip /2.

Even better, have a look at the fixed point packages that make the bit numbers more easy to understand.

eg:

signal ip : sfixed(7 downto 0);
signal op : sfixed(6 downto -1);

op <= ip; (/2 implicit in the data type)

---------- Post added at 11:10 ---------- Previous post was at 11:09 ----------

This shows that in most circumstances, divide by 2^n is actually free (its just connecting wires together).

 

[fanwel]

Hi TrickyDicky,

I get your point. I will try it and will let you know if I get a problems.
Thanks for reply.

 

[fanwel]

Hi TrickyDicky,

For the addition operation, can I write the code using '+' symbol or I need to use lpm_add_sub?

 

[TrickyDicky]

you can use + for signed, unsigned and integer types.

 

[fanwel]

Hi TrickyDicky,

That means I can't use '+' for fixed point. Did you have idea on how to do the addition process?
I have write the division part using fixed point packages. Thank for reply

 

[TrickyDicky]

sorry, + is fine for fixed point too. You can use any of the functions in the package.

 

[fanwel]

Hi TrickyDicky,

Thanks for your helps..

 

[fanwel]

Hi TrickyDicky,

I have write the vhdl code for the addition and division ((A+B)/2) algorithm using fixed point package and the output range is (7 downto -1). Now, in the same stage I write for the subtractor (A-B) algorithm and the output range is (8 downto 0). My problems is I want the output come out one by one (single output). How to declare the output range for the main code since both of the output algorithms are not in the same range?

 

[TrickyDicky]

you will have to make sure they both have the same output bits. In this case, you probably want (8 downto -1). The a+b/2 will have bit 8 always set to '0', and a-b will always have bit -1 set to '0'.

 

[fanwel]

Hi TrickyDicky,

Sorry, what do you mean "The a+b/2 will have bit 8 always set to '0', and a-b will always have bit -1 set to '0'"?
Thank for reply

 

[TrickyDicky]

you would do it like this:

signal a,b,c,d : ufixed(7 downto 0);
signal temp1 : ufixed(8 downto 0);
signal temp2 : ufixed(8 downto 0);

signal op1, op2 : ufixed(8 downto -1);

temp1 <= a + b;  
op1 <= '0' & temp1; --does a divide by 2 implicitly by type declaration

temp2 <= a - b; -- - always increases bit size
op2 <= temp2 & '0';

So now op1 and op2 are correct and have the same array size.

 

[fanwel]

HI TrickyDicky,

Is it the code is synthesis and can be implement in FPGA?
Thanks for reply

 

[TrickyDicky]

yes and yes.

 

[fanwel]

HI TrickyDicky,

Thanks for your helps..

---------- Post added at 13:16 ---------- Previous post was at 13:09 ----------

Sorry again, how to know the code is synthesis and can be implemented? Can you suggest any document to learn more on this?
Thank you

 

[TrickyDicky]

Arithmetic functions for bit types are all synthesisable. The questions we have here are either very basic or just a rewire.

Have a look at this book: VHDL for Logic Synthesis: Amazon.co.uk: Andrew Rushton: Books

 

[fanwel]

Hi TrickyDicky,

Thank you very much!