scan insertion is something which is an obsolete idea when the tools didn't handle scan during normal synthesis. One used to synthesize the Verilog netlist with non-scannable flops. then the flops were replaced by their scan versions (scan insertion)...and connect the scan_in,scan_en etc. This was older way of things. these days the tools take in scan-flops and do the optimization which is scan synthesis ( optimizing the scan chain also along with the logic). scan insertion is an older and obsolete concept.