Design Compiler warnings

[shravan61]

Hi,
opened design vision tool and read Verilog file(ISCAS89 benchmark circuit).
The following script was run inorder to compile

read_verilog dff.v
read_verilog s5378.v
link
check_design
uniquify
set verilogout_no_tri true
set_fix_multiple_port_nets -all -buffer_constants
compile
change_name -hier -rule verilog
write -format verilog -hier -out 2006.06.vg

It gives the warnings as shown in error message.

Warning: In design 's5378', a pin on submodule 'dff_172' is connected to logic 1 or logic 0. (LINT-32) Pin 'd' is connected to logic 1.
Warning: In design 's5378', output port 'po_2935' is connected directly to 'logic 1'. (LINT-52)
Warning: In design 's5378', output port 'po_2636' is connected directly to 'logic 1'. (LINT-52)
Warning: In design 's5378', output port 'po_2634' is connected directly to 'logic 1'. (LINT-52)

For some other circuits I get warnings such as "Some nets doesn't have loads (LINT-1)" and "dff have same net as input and output (LINT-33)". LINT-33 is possible but my orginial design is not like this.

I have no idea why design compiler does such crazy modifications? I would really appreciate it if some body can help me with this?

SG


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[seu_noop]

i think that these optimizations are from your design.you can check your netlist and check which port is tied high or low. then trace back to the rtl. you can find why the dc optimize the rtl.

 

[shravan61]

read_verilog dff.v
read_verilog s5378.v
link
check_design
uniquify
set verilogout_no_tri true
set_fix_multiple_port_nets -all -buffer_constants
compile
change_name -hier -rule verilog
write -format verilog -hier -out 2006.06.vg

The above commands explain whatever the optimization that I have done. I used the same commands for some other circuits. It worked well. But I am facing warnings with few other circuits.

 

[pgbackup]

Such warnings are not a problem. The linter is just indicating that certain signals are permanently connected to VDD/GND. When you compile, design compiler will optimize them (known as satisfiability dont-care conditions) and remove the associated logic.

You should run 'check_design' before doing the 'write' to check for potential problems. If there are, they need to be fixed in RTL or adjust the scripts.

 

[shravan61]

Can you please give me an example of how to adjust scripts?