Design compiler disables some clk to q timing paths

[anssprasad]

Hi,

I have used dftadvisor to insert a scan chain in the design. After scan chain insertion when I read the design netlist into DC and ran a compile it disabled some clock to q timing arcs saying that it found a timing loop. Can anyone explain why this could be happening or even when does DC in general do such disabling of the timing arcs.

Thanks
Prasad.