Deep submicron timing closure challenges

[vijay.mani884]

Dear All,

Kindly discuss your experiences. I want to know what are the major challenges that we may face while closing the time in deep submicron technology. Like 65 nm to 45nm and 45 nm to 28 nm.

I Know cross talk is one big challange. I want to know few other and their remedies.

Thanks in advance for sharing your views.

Cheers

 

[Prashanth.vinnakota]

The major problem you encounter is Leakage Power Dissipation.

Below 65nm Leakage Power dominates Dynamic Power.

Also routing and placement becomes difficult while coming down in feature size.

 

[vijay.mani884]

thats fine how does it effect the timing? well, I know this is also one big challenge, but i am more interested in terms of timing. Thanks for your comment though.

Cheers

 

[Prashanth.vinnakota]

Yeah. I just mentioned the other challenge faced when we keep scaling the technology. Anyhow power consumption will not affect the timing to any extent.

 

[neetendra1]

Hi,
Yes even power is off big concern when considering the Timing as it can result in Forming a Design Timing corner.


Rdgs