aminpix
Advanced Member level 4
I am trying to connect virtex-5 to DDR2. It is my first time doing this. I know the hardware doesn't have any problem. I compile the code (with no error) and program the FPGA, but phy_init_done never goes high !
This code is only reset the RAM and wait till phy_init_done goes high (which never goes high). My input clock is 100MHz
Anybody can help me about it.
I would appreciate if anybody has any sample DDR2 to Virtex (MIG-3.6) code in ISE and share with me.
Here is my code:
This code is only reset the RAM and wait till phy_init_done goes high (which never goes high). My input clock is 100MHz
Anybody can help me about it.
I would appreciate if anybody has any sample DDR2 to Virtex (MIG-3.6) code in ISE and share with me.
Here is my code:
HTML:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Main_unit is
Port ( CLK_100M_P : in STD_LOGIC;
CLK_100M_N : in STD_LOGIC;
LED_01 : out STD_LOGIC;
LED_02 : out STD_LOGIC;
LED_03 : out STD_LOGIC;
LED_04 : out STD_LOGIC;
-----DDR2 Interface
ddr2_dq : inout std_logic_vector(63 downto 0);
ddr2_a : out std_logic_vector(13 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_dqs : inout std_logic_vector(7 downto 0);
ddr2_dqs_n : inout std_logic_vector(7 downto 0);
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0)
);
end Main_unit;
architecture Behavioral of Main_unit is
COMPONENT DCMCLK
PORT(
CLKIN_IN : IN std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic;
CLK90_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
component DDR2RAM
port (
ddr2_dq : inout std_logic_vector(63 downto 0);
ddr2_a : out std_logic_vector(13 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
locked : in std_logic;
rst0_tb : out std_logic;
clk0 : in std_logic;
clk0_tb : out std_logic;
clk90 : in std_logic;
clkdiv0 : in std_logic;
clk200 : in std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector(127 downto 0);
app_wdf_data : in std_logic_vector(127 downto 0);
ddr2_dqs : inout std_logic_vector(7 downto 0);
ddr2_dqs_n : inout std_logic_vector(7 downto 0);
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0)
);
end component;
----------------------------------------------------
signal CLK_100M : STD_LOGIC := '0' ;
signal sys_rst_n : STD_LOGIC := '0' ;
signal phy_init_done : STD_LOGIC := '0' ;
signal locked : STD_LOGIC := '0' ;
signal rst0_tb : STD_LOGIC := '0' ;
signal clk0 : STD_LOGIC := '0' ;
signal clk0_tb : STD_LOGIC := '0' ;
signal clk90 : STD_LOGIC := '0' ;
signal clkdiv0 : STD_LOGIC := '0' ;
signal clk200 : STD_LOGIC := '0' ;
signal app_wdf_afull : STD_LOGIC := '0' ;
signal app_af_afull : STD_LOGIC := '0' ;
signal rd_data_valid : STD_LOGIC := '0' ;
signal app_wdf_wren : STD_LOGIC := '0' ;
signal app_af_wren : STD_LOGIC := '0' ;
signal app_af_addr : STD_LOGIC_VECTOR(30 downto 0) := (others => '0') ;
signal app_af_cmd : STD_LOGIC_VECTOR(2 downto 0) := (others => '0') ;
signal rd_data_fifo_out : STD_LOGIC_VECTOR(127 downto 0) := (others => '0') ;
signal app_wdf_data : STD_LOGIC_VECTOR(127 downto 0) := (others => '0');
type t_SM_Main is (s_Idle, s_ddr2_init_00, s_00, s_01, s_02, s_03, s_03n5, s_04, s_04n5, s_05, s_06, s_07, s_08, s_09, s_10);
signal r_SM_Main : t_SM_Main := s_Idle;
signal tmp_CNTR : STD_LOGIC_VECTOR(40 downto 0);
begin
IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT"
)
port map (
O => CLK_100M, -- clock buffer output
I => CLK_100M_P, -- diff_p clock buffer input
IB => CLK_100M_N -- diff_n clock buffer input
);
u_DDR2RAM : DDR2RAM
port map (
ddr2_dq => ddr2_dq,
ddr2_a => ddr2_a,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_cs_n => ddr2_cs_n,
ddr2_odt => ddr2_odt,
ddr2_cke => ddr2_cke,
sys_rst_n => sys_rst_n,
phy_init_done => phy_init_done,
locked => locked,
rst0_tb => rst0_tb,
clk0 => clk0,
clk0_tb => clk0_tb,
clk90 => clk90,
clkdiv0 => clkdiv0,
clk200 => clk200,
app_wdf_afull => app_wdf_afull,
app_af_afull => app_af_afull,
rd_data_valid => rd_data_valid,
app_wdf_wren => app_wdf_wren,
app_af_wren => app_af_wren,
app_af_addr => app_af_addr,
app_af_cmd => app_af_cmd,
rd_data_fifo_out => rd_data_fifo_out,
app_wdf_data => app_wdf_data,
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n
);
Inst_DCMCLK: DCMCLK PORT MAP(
CLKIN_IN => CLK_100M,
CLK0_OUT => clk0,
CLK2X_OUT => clk200,
CLK90_OUT => clk90,
LOCKED_OUT => locked
);
LED_01 <= '0' ;
LED_02 <= locked ;
LED_04 <= phy_init_done ;
process(clk200)
begin
if (rising_edge(CLK_100M)) then
case r_SM_Main is
when s_Idle =>
LED_03 <= '1' ;
sys_rst_n <= '0' ;
if tmp_CNTR(30)= '0' then
tmp_CNTR <= tmp_CNTR + "0000000000001" ;
elsif tmp_CNTR(30)= '1' then
tmp_CNTR <= (others => '0') ;
r_SM_Main <= s_ddr2_init_00 ;
else
tmp_CNTR <= (others => '0') ;
end if ;
when s_ddr2_init_00 =>
sys_rst_n <= '1' ;
LED_03 <= '0' ;
when others =>
end case;
end if;
end process;
end Behavioral;