Custom Layout: Issue with grouped PMOS devices

[NiedeLu]

Hi,
I have a problem concerning layout. My PMOS transistors are P-cells and are grouped depending on there function. Every group shares a NWELL and an isolation ring (PTAP and DNW). The NWELL should be taped to VDD near every transistor to get proper bulk connections. This is how i wanted to do it. But...

Now my problem:
If I draw an NWELL over a group of PMOS inside a iso-ring, ADS (Layout XL) says that there are shorts from the drains of the devices to the NWELL (VDD). I have no clue why this happens. There is an diode between D and NWELL (biased to VDD). Any suggestions on this? Tool issue? Do i miss something?

I'm not an experienced layout engineer..

Kindly asking for help. BR,
Lukas

 

[erikl]

... an isolation ring (PTAP and DNW).

PTAP and DNW? PTAP not in the DNW, hopefully. It's not clear. Could you pls. clarify, possibly showing schematic and/or layout?

 

[NiedeLu]

PTAP and DNW? PTAP not in the DNW, hopefully. It's not clear. Could you pls. clarify, possibly showing schematic and/or layout?

Thx for your reply. Please have a look at the example picture.

 

[smilodon]

Thx for your reply. Please have a look at the example picture.

You didnt used dnw correctly！DNW commonly are used to isolate a clean psub from the whole substrate and it is not for pmos! NMOS are surrounded with ptap connected to VSS， ntap connected to VDD
surround ptap! Of coure, you must overlap nwell above DNW.
PMOS' bulk should be connected to VDD or other POWER via ntap！

 

[erikl]

looks like your ntap diffusion either contacts or is connected to the channel diffusion.

If this should be the case, it would actually be a short circuit between the channel and VDD (ntaps are connected to VDD).

 

[rangermad]

Nothing obvious in the pic. Are you DRC clean?

 

[NiedeLu]

Thanks for the reply:

Yeah it looks like. On metal there is for sure no connection. How can there be a connection if I have the P-implant/diffusion that forms P+ and N-implant/diffusion that forms N+ inside a NWELL?

- - - Updated - - -

Nothing obvious in the pic. Are you DRC clean?

For me this short connections make no sense. Yes DRC is clean.
P.S.: The Annotation Browser in ADS (Layout XL) is showing the shorts.

Edit: Error message: Overlap of an rectangle on 'NWELL drawing' and instance 'xx' with pin 'D' on net 'xx' creates a short.

 

[erikl]

... How can there be a connection if I have the P-implant/diffusion that forms P+ and N-implant/diffusion that forms N+ inside a NWELL?

Actually these are P- and N- regions which touch or overlap each other. Physically this doesn't matter if correctly biased (which is the case).

For me this short connections make no sense.
Error message: Overlap of an rectangle on 'NWELL drawing' and instance 'xx' with pin 'D' on net 'xx' creates a short.

But ... some PDK systems simply don't allow it. Try to keep some distance between these implant regions. Probably you must respect a minimum spacing rule to then avoid DRC errors.

 

[NiedeLu]

Actually these are P- and N- regions which touch or overlap each other. Physically this doesn't matter if correctly biased (which is the case).



But ... some PDK systems simply don't allow it. Try to keep some distance between these implant regions. Probably you must respect a minimum spacing rule to then avoid DRC errors.

Good morning,
I thought if I have an diffusion layer that shares area with a P-implant I get P+ at the shared area. Without diffusion I get P-. Is that wrong? :roll:
Edit: the white lines are the NWELLs. Pink is P-implant. Gray is N-implant (hard to see on the picture).

My DRC is clean. There are distances to keep between P and N-implant as I did. Is this Annotation Browser a reliable tool?

Thanks for you help guys!

 

[rangermad]

Your + and - are a little confusing to me. Generally a + means a highly doped region such as P diffusion and N diffusion of transistors. So a pmos transistor needs a diffusion region overlapped by a P+ implant.

A minus usually means a well or bulk/substrate. These areas, generally speaking, don't get a separate implant mask.

So yes, this may be wrong.

I thought if I have an diffusion layer that shares area with a P-implant I get P+ at the shared area. Without diffusion I get P-. Is that wrong?

The diffusion layer is just a thinning of the oxide. You need some type of implant layer to change the nwell (N-) to P+ diffusion. P+ implant is that layer.

Looking at the pic again, what is that white box that covers the two inner transistors but no the two dummies?

 

[erikl]

I thought if I have a diffusion layer that shares area with a P-implant I get P+ at the shared area. Without diffusion I get P-. Is that wrong?

Essentially, no. Actually you have an active area (your diffusion area) which gets 1) a P+ implant (in the previously already diffused NWELL area) for the source and drain areas. Then follow 2) an N+ implant for the NWELL contact areas.

the white lines are the NWELLs. Pink is P-implant. Gray is N-implant (hard to see on the picture).

I'd think gray would mark the NWELL border. The 4 white internal rectangles or the 4 pink/magenta rectangles simply could mark the transistor borders. And what would the thin-line inner white rectangle mark?

What's the blue color? Can't be P+ because it covers the whole transistor. Metal_1 either, because this wouldn't make sense. Can't understand it's meaning.

The 8 contacts on top and bottom of the transistors should be gate contacts over poly. Underlying N+ bulk tap contact would be ok - but why would it connect to the channel region? Or is that all N+ tap and (resp. or) poly contact - with the same cross-hatched color areas as the N+ taps. Same for all transistors. To be used alternatively as bulk or as poly gate contact.

From the red color I can't differentiate between P+ and N+ implants - looks the same - at least for me. Internal of the NWELL these would be the N+ taps over and below the transistor regions, to be connected to VDD, the 8 additional N+ bulk taps on top and bottom of the transistors (those not used for gate connections) to be connected to their sources and to their common bulk voltage (VDD), the outer ring P+ taps on substrate to be connected to GND of course.

There are distances to keep between P and N-implant as I did.

Seems so - otherwise you'd got DRC errors.

Is this Annotation Browser a reliable tool?

I don't know, but usually the tool is not responsible for error messages - rules are.
Your error message quite probably stems from an electrical rule violation. Perhaps this can give you an idea - I can't find the reason without a better understanding of your layout layers. And now the metal connection(s) could give an idea.

 

[NiedeLu]

First of all.. thanks for your reply.

I want to clarify the layers:
1) Red - Diffusion
2) Blue - Poly
3) Turquoise - Contact
4) Pink/Magenta - P Implant
5) Gray (hard to see -> around NTAP; over and under PMOS devices) - N Implant
6) White - NWELL
7) thin White (covers inner devices) - DNW

- - - Updated - - -

Your + and - are a little confusing to me. Generally a + means a highly doped region such as P diffusion and N diffusion of transistors. So a pmos transistor needs a diffusion region overlapped by a P+ implant.

A minus usually means a well or bulk/substrate. These areas, generally speaking, don't get a separate implant mask.

So yes, this may be wrong.


The diffusion layer is just a thinning of the oxide. You need some type of implant layer to change the nwell (N-) to P+ diffusion. P+ implant is that layer.

Looking at the pic again, what is that white box that covers the two inner transistors but no the two dummies?

I can see what you mean and I know what the function of + and - is. To connect bulk/substrate you also need + to get a low ohmic connection. In this PDK the layer definition really confuses me.. I think that If I have a P Implant layer in a NWELL I get P- and when there is also a Diffusion layer (not covered by Poly) this P- turns into P+ (Source and Drain). The active area is formed where Diffusion is covered by Poly. For me the output of Diffusion is always a + Region. Please correct me if I'm wrong.

- - - Updated - - -

Essentially, no. Actually you have an active area (your diffusion area) which gets 1) a P+ implant (in the previously already diffused NWELL area) for the source and drain areas. Then follow 2) an N+ implant for the NWELL contact areas.



I'd think gray would mark the NWELL border. The 4 white internal rectangles or the 4 pink/magenta rectangles simply could mark the transistor borders. And what would the thin-line inner white rectangle mark?

What's the blue color? Can't be P+ because it covers the whole transistor. Metal_1 either, because this wouldn't make sense. Can't understand it's meaning.

The 8 contacts on top and bottom of the transistors should be gate contacts over poly. Underlying N+ bulk tap contact would be ok - but why would it connect to the channel region? Or is that all N+ tap and (resp. or) poly contact - with the same cross-hatched color areas as the N+ taps. Same for all transistors. To be used alternatively as bulk or as poly gate contact.

From the red color I can't differentiate between P+ and N+ implants - looks the same - at least for me. Internal of the NWELL these would be the N+ taps over and below the transistor regions, to be connected to VDD, the 8 additional N+ bulk taps on top and bottom of the transistors (those not used for gate connections) to be connected to their sources and to their common bulk voltage (VDD), the outer ring P+ taps on substrate to be connected to GND of course.




Seems so - otherwise you'd got DRC errors.




I don't know, but usually the tool is not responsible for error messages - rules are.
Your error message quite probably stems from an electrical rule violation. Perhaps this can give you an idea - I can't find the reason without a better understanding of your layout layers. And now the metal connection(s) could give an idea.

The inner white rectangles are NWELLs and pink are P implants as the devices are automatically generated P-cells. I have just drawn a NWELL around them to use a shared NWELL for all devices. Actually the W/L ratios of my devices are very small (Wmin) therefore they look a little bit "strange". As I understand Diffusion (red) can in combination with a P-implant be a P+ or in combination with a N-implant be a N+.

With metal, 2x Dummy

 

[rangermad]

7) thin White (covers inner devices) - DNW

deep nwell or some type of diode recognition layer? Why do you need this?

 

[erikl]

1) Red - Diffusion
2) Blue - Poly
3) Turquoise - Contact <--- M1, I'd think. Isn't contact green?
4) Pink/Magenta - P Implant <--- No, I think this is just the P-cell edge.
5) Gray (hard to see -> around NTAP; over and under PMOS devices) - N Implant
6) White - NWELL
7) thin White (covers inner devices) - DNW

- - - Updated - - -

I think that If I have a P Implant layer in a NWELL I get P-

A P implant usually creates a P+ region, a P- region isn't necessary for pMOSFETs in NWELL (it is created in the channel by gate control).

... and when there is also an active area (not covered by Poly) this NWELL region turns into P+ (Source and Drain) by a p+ implant. The channel region is formed where P+ region is covered by Poly. For me the output of an implant is always a + Region. Please correct me if I'm wrong.

Done by red.

The inner white rectangles are NWELLs and pink are P-cell edges (s. above) as the devices are automatically generated P-cells. I have just drawn a NWELL around them to use a shared NWELL for all devices. Actually the W/L ratios of my devices are very small (Wmin) therefore they look a little bit "strange". As I understand active area (red) can in combination with a P-implant be a P+ or in combination with a N-implant be a N+.

Pls. check if you think this is correct:

I don't see the VDD connection to the N+ bulk taps, nor to the dummy poly gate connections, BTW.