chip-monk
Newbie level 5
Hi,
The synthesized netlist from Cadence RTL Compiler is in Verilog whereas the library cell definitions (used for gate level simulations) are in VHDL.
Can cadence use both VHDL and Verilog files together?
Thanks.
The synthesized netlist from Cadence RTL Compiler is in Verilog whereas the library cell definitions (used for gate level simulations) are in VHDL.
Can cadence use both VHDL and Verilog files together?
Thanks.