Compiling Verilog and VHDL files together in Cadence

[chip-monk]

Hi,

The synthesized netlist from Cadence RTL Compiler is in Verilog whereas the library cell definitions (used for gate level simulations) are in VHDL.

Can cadence use both VHDL and Verilog files together?


Thanks.

 

[wsong0210]

If I understand your question right, you can use Verilog in RTL compiler for synthesis.
Let RTL compiler output the post-synthesis netlist in VHDL.
Using the VHDL post-syn netlist and the VHDL cell lib to do post-syn simulation should have no further problem.

Anyway, Cadence can handle Verilog and VHDL. In that case, you need to refer to the RTL Compiler's manual for port mapping between VHDL and Verilog.