clock_gating question

[manajel1]

hi,
what control the max_fanout number in Clock-Gating?

thank u.

 

[kalyanasv]

What controls it? It is truly design dependent. From routing, to node size, .....frequency of operation.
At the device level you want to increase fanout you could add buffer.
At the transistor level your looking at transistor sizing.

 

[manajel1]

ok i hunderstand thanks,
in design compiler what is the default value of CG max_fanout?

 

[kalyanasv]

The fan out is not based on design compiler. teh max fan out is based on how you design your transistors i.e. your library. typically the DC fanout for CMOS circuits is very high >10000. Now, synopsys has a power compiler which takes care of clock gating. If your using TTL or HBJT or ...then the fanout would change from 2-3 to thousands.

I am assuming your doing a digital design, if it analog or mixed signal it is different.

 

[lostinxlation]

I think the question is about the max number of flops you let a single clock gating cell deal with.
I thought the default value was 32 or 64, but it might be a min fanout, I don't remember.

Learn to use 'man' command.

 

[michealwolf]

There is an attribute to control the min CG fanout. But why do you want to control the max? It's absolutelly no need to control it.

 

[lostinxlation]

There is an attribute to control the min CG fanout. But why do you want to control the max? It's absolutelly no need to control it.

Having too many flops controlled by a single clock gating cell makes the clock tree starting at a clock gating cell deeper which may end up with setup violations on the clock enabling path. THis is a very common issue with a clock gating.