[SOLVED] Can you help with synopsys ic compiler lvs problem?

[wjoon88]

Hello,

if there is anybody who is familiar with this situation, can you give me an advice??

if i run "verify_lvs", i get this message.

----------------------------------------------------------------------------------------
ERROR : OUTPUT PortInst reg_acc_reg_9_ QN doesn't connect to any net.

ERROR : OUTPUT PortInst reg_acc_reg_8_ Q doesn't connect to any net.

ERROR : OUTPUT PortInst reg_acc_reg_6_ QN doesn't connect to any net.

ERROR : OUTPUT PortInst reg_acc_reg_3_ QN doesn't connect to any net.

ERROR : OUTPUT PortInst reg_acc_reg_0_ QN doesn't connect to any net.

ERROR : OUTPUT PortInst U1595 S doesn't connect to any net.

ERROR : OUTPUT PortInst reg_delayed_barrel_shifter_in_reg_3_ QN doesn't connect to any net.

** Total Floating ports are 7.
** Total Floating Nets are 0.
** Total SHORT Nets are 0.
** Total OPEN Nets are 0.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.
----------------------------------------------------------------------------------------

The errors say that Q or QN of D flip-flops are floating.

But I don't think that it is an error(floating pins of D flip-flops), and also the total electrical equivalent error are 0.

But I really don't understand why the ic compiler say that it is an error.

Is it really lvs error?? or not??

 

[ThisIsNotSam]

probably not. your logic is probably using the Q pin of a flop, but that flop provides both Q and QN. QN is left floating. this is pretty common and benign.

 

[wjoon88]

Thanks for your opinion!

 

[Prashanthanilm]

Not a real LVS.

Few of the Ports might be floating (based on your verilog)

But to confirm this, Run LVS with Calibre (or any sign off) tool